Taiwan-based memory packaging/testing company Powertech Technology (PTI) and wafer foundry United Microelectronics (UMC) as well as Japan-based DRAM maker Elpida Memory on May 30 signed together for collaboration to develop 3D IC logic+DRAM integration technologies for advanced processes of 28nm and below.
The collaboration will integrate Elpida's advanced DRAM technologies, UMC's logic IC foundry technologies and PTI's packaging capabilities to develop a single-chip 3D IC logic+DRAM integration solution using TSV (through silicon via) technology, PTI pointed out. The total solution includes logic+DRAM interface design, TSV formation, wafer thinning, packaging by stacking chips and testing.
The three companies' engineers have been working on joint development of TSV chips at Elpida's fab in Hiroshima, southwestern Japan, and stack packaging and testing of TSV chips at UMC's and PTI's fabs in Taiwan.
Such an integration solution, planned to be offered in 2012, is able to improve logic performance, enhance cost competitiveness and reduce time to market.