Elpida Memory on June 27 announced that it has begun sample shipments of its DDR3 SDRAM (x32-bit I/O configuration) made using TSV stacking technology. The sample is a low-power 8Gb (1GB) DDR3 SDRAM assembled in a single package that consists of four 2Gb DDR3 SDRAMs fitted to a single interface chip using TSV.
Elpida began developing TSV in 2004 based on a grant program hosted by the New Energy and Industrial Technology Development Organization (NEDO), a research endeavor founded by the Japanese government, according to the company. Since then it has continued to develop the technology. The company also claimed that In 2009 it successfully developed the industry's first TSV DRAM based on stacking together eight 1Gb DDR3 SDRAMs.
In the case of notebook PCs, Elpida believes that trial use of its 8-gigabit TSV DRAM samples will demonstrate that compared with systems that use SO-DIMM (Small-outline DIMM), operating power can be reduced by 20% and standby power by 50%. Also, the chip mounting area can be reduced by 70%, the chip height can be decreased and the DIMM socket can be eliminated.
The new TSV DRAM will be presented as an eco-friendly DRAM that can contribute greater energy savings and enable thin notebooks, tablet PCs and other mobile computing systems experiencing rapid market growth to become even smaller, thinner and lighter, Elpida pointed out.
TSV is three-dimensional stack packaging technology, which involves stacking together multiple chips vertically through electrical connections with metal-filled via holes in the SI die. Compared with the existing connection method of wire bonding multiple chips, TSV greatly reduces the length of wires in the semiconductor design to enable faster speeds, lower power consumption, smaller package size and other important chip function advantages.