Memory industry standards body JEDEC Solid State Technology Association has announced selected key attributes of its widely-anticipated DDR4 memory chip standard. With publication forecast for mid-2012, JEDEC DDR4 will represent a significant advancement in performance with reduced power usage as compared to previous generation technologies.
DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products, JEDEC said. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard.
A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage, JEDEC indicated. DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable, the organization added.
The per-pin data rates, over time, will be 1.6GT/s to an initial maximum objective of 3.2GT/s, JEDEC said. With DDR3 exceeding its expected peak of 1.6GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future, JEDEC revealed.
Other performance features planned for inclusion in the DDR4 standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667Mhz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes, JEDEC said. Additional features include three new data width offerings, differential signaling, new termination scheme, data masking and new CRC for data bus.
"Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption," said Joe Macri, chairman of JEDEC's JC-42.3 subcommittee for DRAM memories.