In a major development for the semiconductor industry, the Universal Chiplet Interconnect Express (UCIe) Consortium has released the UCIe 2.0 Specification. This new specification is a comprehensive upgrade that addresses the design challenges of testability, manageability, and debug (DFx) for the System-in-Package (SiP) lifecycle across various chiplets.

A key feature of the UCIe 2.0 Specification is the introduction of optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions. This allows for vendor-agnostic chiplet interoperability, enabling a flexible and unified approach to SiP management and DFx operations.

The specification also supports 3D packaging, which provides higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. UCIe-3D is optimized for hybrid bonding with a functional bump pitch that ranges from 10-25 microns down to as small as 1 micron or less, offering flexibility and scalability.

Furthermore, the UCIe 2.0 Specification includes optimized package designs for interoperability and compliance testing. Compliance testing aims to validate the main-band supported features of a Device Under Test (DUT) against a known-good reference UCIe implementation, establishing an initial framework for physical, adapter, and protocol compliance testing.

Cheolmin Park, UCIe Consortium President and Corporate VP of Samsung Electronics, stated, "The UCIe 2.0 Specification builds on previous iterations by developing a comprehensive solution stack and encouraging interoperability between chiplet solutions. This is yet another example of the Consortium's dedication to the flourishing open chiplet ecosystem."

The UCIe 2.0 Specification is fully backward compatible with UCIe 1.1 and UCIe 1.0, ensuring a seamless transition for existing technologies. It is available to the public by request and represents a significant step forward in the development of chiplet technology, supporting the needs of a rapidly evolving semiconductor industry.