ChipMOS Technology has set aside a capital expenditure budget of US$85 million for 2012, an increase of 10.4% from 2011.

The budget breakdown is 40% to be used on packaging/testing equipment of LCD driver ICs, 30% on bumping equipment and 30% on copper wire bonding, wafer-level packaging and testing equipment, according to SJ Cheng, chairman for ChipMOS.

On the contrary, fellow packaging and testing firms Powertech Technology (PTI) and King Yuan Electronics Company (KYEC) expect their capex for 2012 to be lower than those allocated in 2011, according to the companies.

PTI has revealed plans to shift its focus to non-DRAM products in 2012. Capex for the year will be mainly utilized for developing new packaging technologies for logic semiconductors, the company said previously.

KYEC estimated its 2011 capex at NT$3-4 billion (US$100-133 million), and spending for 2012 would be less than the level.

Siliconware Precision Industries (SPIL) chairman Bough Lin remarked previously that the company would budget about NT$11 billion in capex for 2012, slightly lower than NT$11.5 billion in 2011. Advanced Semiconductor Engineering (ASE) also intends to keep its 2012 capex at around the US$750 million reached in 2011.

ASE, SPIL and PTI are expected to unveil their capex plans for 2012 at their upcoming investors meetings scheduled for February 10, 15 and 9, respectively.