Macronix International has announced that its recent research results will pave the way for the company to develop scalable and efficient 3D NAND flash using its patented BE-SONOS (barrier engineering) charge-trapping technology and 3D decoding architecture.
Macronix reported the fabrication and demonstration of an eight-layer, 75nm half-pitch, 3D VG (vertical gate) NAND flash using a junction-free BE-SONOS scheme in a paper presented at the 2010 Symposium on VLSI Technology earlier this month.
"Traditional NAND flash will be facing technology barrier when it scales to below 2Xnm node" said CY Lu, president of Macronix. "The 3D memory cell array structure has been proposed to be the most promising candidate for NAND flash to shrink to below 1Xnm."
Using 3D stacking, NAND flash may achieve higher data storage capacity and effectively lower fabrication cost without relying on advances in lithography technology, according to Macronix. Several 3D NAND flash structures have been proposed, such as P-BiC(Spipe-shaped bit cost scalable), TCAT(terabit cell array transistor), VSAT (vertical stacked array transistor) and VG.
Macronix said its work has chosen the VG architecture, believing it is the best approach. Simulation shows this structure could be scaled to 25nm node in a 3D array, providing density far beyond conventional 2D NAND Flash.
Macronix expects products that adopt 3D NAND flash technology will be commercialized in 2014.
Previous reports cited Macronix chairman Miin Wu as saying the company plans to deliver samples of its in-house developed NAND chips to potential customers in the first half of 2011, a milestone for Macronix' entry into the NAND flash territory.